1. Field of the Invention
The invention relates to a method for external units of a computer for supplying interrupt request signals without priorities to the central processor unit of the computer via a common control line.
2. Description of the Prior Art
Adam Osborne, Einfuhrung in die Mikrocomputer-tecknik, 1977, describes on pages 5-10 to 5-24 how interrupts are initiated in computer systems.
External units or peripheral apparatus in most computer systems are capable of interrupting the program steps currently being executed in the central processor unit (CPU) of the computer by means of an interrupt request signal. The external units are connected to the central processor unit of the computer via a common control line on which they despatch their interrupt request signals.
The central processor unit acknowledges each individual interrupt request by way of an interrupt acknowledge. For as long as interrupts are not requested simultaneously by more than one external unit, the interruptions are executed consecutively. However, when two or more external units despatch coexistent interrupt request signals on the common control line, the execution of the individual interrupts must somehow be controlled.
Two solutions are known to this problem. One solution consists in that interrupt priorities are assigned to the external units. When the central processor unit simultaneously receives interrupt request signals from several external units, the interrupts are executed in accordance with the priorities assigned to the external units. Thus, external units having requested an interrupt receive the interrupt acknowledgements from the central processor unit in the same order of priorities.
Another known solution in the relevant field is a method without priorities. All external units have the same priority as regards the requesting of interrupts. As in the first solution, the external units are connected to the central processor unit of the computer by means of a common control line on which the interrupt request signals are despatched. From the central processor unit there is only a single line on which the central processor unit returns the interrupt acknowledge and which extends to only one of the external units wherefrom a further line extends to the next unit and so on until the last unit wherefrom no further line extends, so that all units which are capable of requesting an interrupt are directly linked. This is referred to as daisy chaining. The interrupt acknowledge despatched by the central processor unit contains the address of the unit having despatched the interrupt request signal. When the first unit receives the interrupt acknowledge, a logic circuit checks whether the acknowledge contains its own address. If this is not the case, the first unit passes the interrupt acknowledge onto the next unit whose logic circuit then checks whether the interrupt acknowledge contains its own address. If this is so, the interrupt acknowledge will not be passed on to the next unit. Except for the last unit wherefrom no further line extends, therefore, all units should comprise a logic circuit which is capable of detecting whether the interrupt acknowledge contains its own address, and which, if this is not the case, passes the interrupt acknowledge on to the next unit but which does not pass on the interrupt acknowledge to the next unit when it recognizes its own address.
Because the interrupt acknowledge is tested in each unit and may have to be passed on from unit to unit in accordance with the test results, this is a complex method. It is also expensive because each unit with the exception of the last one, requires a logic circuit for address recognition.